A conventional PLL circuit has a phase comparator that makes equal the rectangular wave signal time width of a high voltage level and that of a low voltage level when the output signal of the phase comparison has no phase difference because the time difference between the time width of the high voltage level rectangular wave signal and the time width of the low voltage level rectangular wave signal is proportional to the phase difference. In addition, it omits a loop filter that has been necessary previously, and has, at a portion in which the loop filter is mounted in a prior PLL circuit, a waveform shaping circuit that operates in such a manner that the output signal waveform from the phase comparator circuit holds a rectangular shape (see Patent Document 1, for example).
Patent Document 1: Japanese patent application laid-open No. 2004-40227.
With the foregoing configuration, as for the phase difference between the reference clock signal and the comparison clock signal, the conventional PLL circuit can eliminate the phase difference within the phase comparison period. As for the frequency difference between the reference clock signal and the comparison clock signal, however, it has a problem in that the frequency of the comparison clock signal, that is, the frequency of the output clock signal of a voltage controlled oscillator, varies within the phase comparison period.
In addition, in a design method of the conventional PLL circuit, there is a problem in that since the frequency of the output clock signal varies, it is difficult to make the numerical expression of the capturing process of the frequency.
The present invention is implemented to solve the foregoing problems. Therefore it is an object of the present invention to provide a PLL circuit with small output frequency fluctuations in the steady state.
Another object of the present invention is to provide a design method of the PLL circuit capable of designing a high performance PLL circuit with easy circuit response analysis.